View ATMEGA128RFA1_4861253.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ATMEGA128RFA1
Features
* High Performance, Low Power AVR 8-Bit Microcontroller * Advanced RISC Architecture - 135 Powerful Instructions - Most Single Clock Cycle Execution - 32x8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz and 1.8V - On-Chip 2-cycle Multiplier * Non-volatile Program and Data Memories - 128K Bytes of In-System Self-Programmable Flash * Endurance: 2000 Write/Erase Cycles @ 85 C - 4K Bytes EEPROM * Endurance: 2000 Write/Erase Cycles @ 85 C - 16K Bytes Internal SRAM * JTAG (IEEE std. 1149.1 compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface * Peripheral Features - Multiple Timer/Counter & PWM channels - Real Time Counter with Separate Oscillator - 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor - Master/Slave SPI Serial Interface - Two Programmable Serial USART - Byte Oriented 2-wire Serial Interface * Advanced Interrupt Handler * Watchdog Timer with Separate On-Chip Oscillator * Power-on Reset and Low Current Brown-Out Detector * Advanced Power Save Modes * Fully integrated Low Power Transceiver for 2.4 GHz ISM Band - Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s - -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm - Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry) - 32 Bit IEEE 802.15.4 Symbol Counter - Baseband Signal Processing - SFR-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation - Antenna Diversity and TX/RX control - TX/RX 128 Byte Frame Buffer * Hardware Security (AES, True Random Generator) * Integrated Crystal Oscillators (32.768 kHz & 16 MHz) * I/O and Package - 38 Programmable I/O Lines - 64-pad QFN (RoHS/Fully Green) * Temperature Range: -40 to 85 Industrial C C * Supply voltage range 1.8V to 3.6V with integrated voltage regulators * Ultra Low Power consumption (1.8 to 3.6V) for Rx/Tx & AVR: <18.6 mA - CPU Active Mode (16MHz): 4.1 mA - 2.4GHz Transceiver: RX_ON 12.5 mA / TX 14.5 mA (maximum TX output power) - Deep Sleep Mode: <250nA @ 25 C * Speed Grade: 0 - 16 MHz @ 1.8 - 3.6V
(R)
8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4 ATMEGA128RFA1
PRELIMINARY
Applications
* ZigBee / IEEE 802.15.4-2006/2003TM - Full And Reduced Function Device (FFD/RFD) * General Purpose 2.4GHz ISM Band Transceiver with Microcontroller * RF4CE, SP100, WirelessHARTTM, ISM Applications and IPv6 / 6LoWPAN
(R)
8266AS-MCU Wireless-12/09
1
8266AS-MCU Wireless-12/09
1 Pin Configurations
Figure 1-1. Pinout ATMEGA128RFA1
[PE7:ICP3:INT7:CLKO]
[XTAL1]
[AVDD]
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 [PF2:ADC2:DIG2] 1 [PF3:ADC3:DIG4] 2 [PF4:ADC4:TCK] 3 [PF5:ADC5:TMS] 4 [PF6:ADC6:TDO] 5 [PF7:ADC7:TDI] 6 [AVSS_RFP] 7 [RFP] 8 [RFN] 9 [AVSS_RFN] 10 [TST] 11 [RSTN] 12 [RSTON] 13 [PG0:DIG3] 14 [PG1:DIG1] 15 [PG2:AMR] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0 0 [PD0:SCL:INT0] [PD3:TXD1:INT3] [PD1:SDA:INT1] [PD2:RXD1:INT2] [DVSS:DSVSS] [PG3:TOSC2] [PG4:TOSC1] [PG5:OC0B] [PD5:XCK1] [PD4:ICP1] [PD6:T1] [DEVDD] [PD7:T0] [DVDD] [DVDD] [DVSS] Exposed paddle: [AVSS] Index corner 48 [PE2:XCK0:AIN0] 47 [PE1:TXD0] 46 [PE0:RXD0:PCINT8] 45 [DVSS] 44 [DEVDD]
[PE3:OC3A:AIN1] 43 [PB7:OC0A:OC1C:PCINT7] 42 [PB6:OC1B:PCINT6] 41 [PB5:OC1A:PCINT5] 40 [PB4:OC2A:PCINT4] 39 [PB3:MISO:PDO:PCINT3] 38 [PB2:MOSI:PDI:PCINT2] 37 [PB1:SCK:PCINT1] 36 [PB0:SSN:PCINT0] 35 [DVSS] 34 [DEVDD] 33 [CLKI]
[PE5:OC3C:INT5]
ATMEGA128RFA1
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization results of other AVR microcontrollers and radio transceivers manufactured in a similar process technology. Minimum and Maximum values will be available after the device is characterized.
2
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
[PE4:OC3B:INT4]
[AVSS:ASVSS]
[PE6:T3:INT6]
[PF1:ADC1]
[PF0:ADC0]
[DEVDD]
[XTAL2]
[EVDD]
[AVSS]
[DVSS]
[AREF]
ATMEGA128RFA1
3 Overview
The ATMEGA128RFA1 is a low-power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band. It is derived from the ATmega1281 microcontroller and the AT86RF231 radio transceiver. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication.
3.1 Block Diagram
Figure 3-1 Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two independent registers can be accessed with one single instruction executed in one clock cycle. The resulting architecture is very code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The system includes internal voltage regulation and an advanced power management. Distinguished by the small leakage current it allows an extended operation time from battery. The radio transceiver is a fully integrated ZigBee solution using a minimum number of external components. It combines excellent RF performance with low cost, small size and low current consumption. The radio transceiver includes a crystal stabilized fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread
3
8266AS-MCU Wireless-12/09
Spectrum Signal (DSSS) processing with spreading and despreading. The device is fully compatible with IEEE802.15.4-2006/2003 and ZigBee standards. The ATMEGA128RFA1 provides the following features: 128 kbytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 4 kbytes EEPROM, 16 kbytes SRAM, up to 35 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), 6 flexible Timer/Counters with compare modes and PWM, USART, a byte oriented 2-wire Serial Interface, a 8 channel, 10 bit analog to digital converter (ADC) with an optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, a SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and 6 software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the RC oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main RC oscillator and the asynchronous timer continue to run. Typical supply current of the microcontroller with CPU clock set to 16MHz and the radio transceiver for the most important states is shown in the Figure 3-2 below. Figure 3-2 Radio transceiver and microcontroller (16MHz) supply current
20 1.8V 3.0V 3.6V I(DEVDD,EVDD) [mA] 15 16,6mA 18,6mA
10 4,7mA
5 250nA
Deep Sleep
4,1mA
0
SLEEP
TRX_OFF
RX_LISTEN
TX_ACT
Radio Transceiver State
The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode the current is dissipated by the AVR microcontroller only. In Deep Sleep mode all major digital blocks with no data retention requirements are disconnected from main supply providing a very small leakage current. Watchdog timer, MAC symbol counter and 32.768kHz oscillator can be configured to continue to run. The device is manufactured using Atmel's high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system 4
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
ATMEGA128RFA1
trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by on on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the boot Flash section will continue to run while the application Flash section is updated, providing true Read-While-Write operation. By combining an 8 bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATMEGA128RFA1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATMEGA128RFA1 AVR is supported with a full suite of program and system development tools including: C compiler, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
3.2 Pin Descriptions
3.2.1 EVDD External analog supply voltage; 3.2.2 DEVDD External digital supply voltage; 3.2.3 AVDD Regulated analog supply voltage (internally generated); 3.2.4 DVDD Regulated digital supply voltage (internally generated); 3.2.5 DVSS Digital ground; 3.2.6 AVSS Analog ground; 3.2.7 Port B (PB7...PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also provides functions of various special features of the ATMEGA128RFA1. 3.2.8 Port D (PD7...PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also provides functions of various special features of the ATMEGA128RFA1. 3.2.9 Port E (PE7...PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also provides functions of various special features of the ATMEGA128RFA1.
5
8266AS-MCU Wireless-12/09
3.2.10 Port F (PF7...PF0) Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port F also provides functions of various special features of the ATMEGA128RFA1. 3.2.11 Port G (PG5...PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. However the driver strength of PG3 and PG4 is reduced compared to the other port pins. The output voltage drop (VOH, VOL) is higher while the leakage current is smaller. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also provides functions of various special features of the ATMEGA128RFA1. 3.2.12 AVSS_RFP AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port. 3.2.13 AVSS_RFN AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port. 3.2.14 RFP RFP is the positive terminal for the bi-directional, differential RF I/O port. 3.2.15 RFN RFN is the negative terminal for the bi-directional, differential RF I/O port. 3.2.16 RSTN Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. 3.2.17 RSTON Reset output. A low level on this pin indicates a reset initiated by the internal reset sources or the pin RSTN. 3.2.18 XTAL1 Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver. 3.2.19 XTAL2 Output of the inverting 16MHz crystal oscillator amplifier; 3.2.20 AREF Reference voltage output of the A/D Converter. In general this pin is left open. 3.2.21 TST Programming and test mode enable pin; 3.2.22 CLKI Input to the clock system. If selected, it provides the operating clock of the microcontroller.
3.3 Compatibility to ATmega1281/2561
The basic AVR feature set of the ATMEGA128RFA1 is derived from the ATmega1281/2561. Address locations and names of the implemented modules and 6
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
ATMEGA128RFA1
registers are unchanged as long as it fits the target application of a very small and power efficient radio system. In addition, several new features were added. Backward compatibility of the ATMEGA128RFA1 to the ATmega1281/2561 is provided in most cases. However some incompatibilities between the microcontrollers exist. 3.3.1 Port A and Port C Port A and Port C are not implemented. The associated registers are available but will not provide any port control. Remaining ports are kept at their original address location to not require changes of existing software packages. 3.3.2 External Memory Interface The alternate pin function "External Memory interface" using Port A and Port C is not implemented due to the missing ports. The large internal data memory (SRAM) does not require an external memory and the associated parallel interface. It keeps the system radiation (EMC) at a very small level to provide very high sensitivity at the antenna input. 3.3.3 High Voltage Programming Mode Alternate pin function BS2 (high voltage programming) of pin PA0 is mapped to a different pin. Entering the parallel programming mode is controlled by the TST pin. 3.3.4 AVR Oscillators and External Clock The AVR microcontroller can utilize the high performance crystal oscillator of the 2.4GHz transceiver connected to the pins XTAL1 and XTAL2. An external clock can be applied to the microcontroller using the clock input CLKI. 3.3.5 Analog Frontend The ATMEGA128RFA1 has a new A/D converter. Software compatibility is basically assured. Nevertheless to benefit from the higher conversion speeds and the better performance some changes are required.
7
8266AS-MCU Wireless-12/09
4 Application Circuits
4.1 Basic Application Schematic
A basic application schematic of the ATMEGA128RFA1 with a single-ended RF connector is shown in Figure 4-1 below. The 50 single-ended RF input is transformed to the 100 differential RF port impedance using Balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, capacitor C4 improves matching. Figure 4-1. Basic Application schematic (Table 4-1 on page 9)
CX1 CB2 VDD CR1 64 1 2 3 4 5 6 PF7 C1 RF B1 C4 C2 7 AVSS 8 RFP 9 RFN 10 AVSS 11 TST 12 RSTN 13 RSTON 14 PG0 DEVDD 15 DVDD DVDD DVSS PG5 16 17 18 63 PF0 62 AREF CB1 61 60 AVDD AVSS 59 EVDD 58 AVSS 57 XTAL1 56 XTAL2 55 DVSS 54 DEVDD 53 PE7 52 51 50 49 48 47 PE0 46 DVSS 45 DEVDD 44 PB7 43 42 XTAL CX2
ATMEGA128RFA1
41 40 39 38 37 PB0 36 DVSS 35 DEVDD 34
DVSS
PD0
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CX3
XTAL 32kHz
CB3 CX4
CB4
VDD
The power supply bypass capacitors (CB2, CB4) are connected to the external analog supply pin (EVDD, pin 59) and external digital supply pin (DEVDD, pin 23). Pins 34, 44 and 54 supply the digital port pins. Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation and to improve noise immunity. Capacitors should be placed as close as possible to the pins and should have a lowresistance and low-inductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the 16MHz crystal oscillator for the 2.4GHz
8
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
PD7
33 CLKI
ATMEGA128RFA1
transceiver. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances must be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes. The 32.768 kHz crystal connected to the internal low power (sub 1A) crystal oscillator provides a stable time reference for all low power modes including 32 Bit IEEE 802.15.4 Symbol Counter ("MAC Symbol Counter") and real time clock application using the asynchronous timer T/C2 ("Timer/Counter2 with PWM and Asynchronous Operation"). Total capacitance including CX3, CX4 should not exceed 15pF on both pins. The very low supply current of the oscillator requires careful layout of the PCB and any leakage path must be avoided. Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins can degrade the system performance. The programming of minimum drive strength settings for the digital output signal is recommended (see "DPDS0 - Port Driver Strength Register 0").
Table 4-1. Example Bill of Materials (BoM) for "Basic Application Schematic" on page 8
Designator B1 Description SMD balun SMD balun / filter LDO VREG bypass capacitor Power supply bypass capacitor Crystal load capacitor RF coupling capacitor Value 2.4 GHz Manufacturer Wuerth Johanson Technology Part Number 748421245 2450FB15L0001 0603YD105KAT2A GRM188R61C105KA12D Comment Filter included X5R (0603) 10% 16V
CB1 CB3 CB2 CB4 CX1, CX2 C1, C2
1 F AVX (100nF minimum) Murata 1 F (100nF minimum) 12 pF 22 pF AVX Murata Epcos Epcos AVX Johnstech
06035A120JA GRP1886C1H120JA01 B37930 B37920 06035A220JAT2A
COG (0603) C0G
5% 5%
50V 50V
(0402 or 0603)
C4 (optional) RF matching R1 XTAL CLKM low-pass filter resistor Crystal
0.47 pF 680
Designed for fCLKM = 1 MHz XWBBPL-F-1 A207-011 Rs=100 kOhm
CX-4025 16 MHz ACAL Taitjen SX-4025 16 MHz Siward
XTAL 32kHz Crystal
4.2 Extended Feature Set Application Schematic
The ATMEGA128RFA1 supports additional features like: * Security Module (AES) * High Data Rate Mode up to 2MBits/s * Antenna Diversity using alternate pin function DIG1/2 at Port G and F * RX/TX Indicator using alternate pin function DIG3/4 at Port G and F An extended feature set application schematic illustrating the use ATMEGA128RFA1 Extended Feature Set, is shown in Figure 4-2 on page 10. of the
9
8266AS-MCU Wireless-12/09
Figure 4-2. Extended Feature Application schematic
CX1 CB2 VDD CR1 64 1 2 3 4 ANT0 5 6 PF7 N2 RFSwitch RFSwitch Balun LNA PA N1 SW1 B1 11 TST ANT1 12 RSTN 13 RSTON 14 PG0 DEVDD 15 DVDD DVDD DVSS PG5 16 17 18 38 37 PB0 36 DVSS 35 DEVDD 34 DVSS PD0 PD7 27 28 29 30 31 32 VDD 33 CLKI SW2 7 AVSS 8 RFP 9 RFN 10 AVSS 63 62 PF0 AREF CB1 61 60 AVDD AVSS 59 EVDD 58 57 AVSS XTAL1 56 55 XTAL2 DVSS 54 DEVDD 53 52 PE7 51 50 49 48 47 PE0 46 DVSS 45 DEVDD 44 PB7 43 42 XTAL CX2
ATMEGA128RFA1
41 40 39
19
20 21
22
23
24
25 26
CX3
XTAL 32kHz
CB3 CX4
CB4
Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations.
10
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
ATMEGA128RFA1
5 Revision history
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision
Rev. 8266AS-MCU Wireless-12/09
1. Initial release
11
8266AS-MCU Wireless-12/09
Table of Contents
1 Pin Configurations.............................................................................. 2 2 Disclaimer............................................................................................ 2 3 Overview .............................................................................................. 3
3.1 Block Diagram ........................................................................................................ 3 3.2 Pin Descriptions...................................................................................................... 5 3.3 Compatibility to ATmega1281/2561 ....................................................................... 6
4 Application Circuits ............................................................................ 8
4.1 Basic Application Schematic .................................................................................. 8 4.2 Extended Feature Set Application Schematic........................................................ 9
5 Revision history ................................................................................ 11 Table of Contents................................................................................. 12
12
ATMEGA128RFA1
8266AS-MCU Wireless-12/09
ATMEGA128RFA1
Disclaimer
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts
Literature Request www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, AVR(R), and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
13
8266AS-MCU Wireless-12/09

▲Up To Search▲

Price & Availability of ATMEGA128RFA1

	To Download ATMEGA128RFA1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .